Japanese Patent Application No. 2000-251436, filed on Aug. 22, 2000, is hereby incorporated by reference in its entirety.
The present invention relates to a memory cell array having ferroelectric capacitors. More particularly, the present invention relates to a simple matrix memory cell array using only ferroelectric capacitors instead of cell transistors, a method of fabricating the same, and a ferroelectric memory device including the memory cell array.
A simple matrix memory cell array using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory cell array has been expected.
An objective of the present invention is to provide: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the same; and a ferroelectric memory device including the memory cell array of the present invention.
According to a first aspect of the present invention, there is provided a first memory cell array having ferroelectric capacitors, wherein:
memory cells formed of ferroelectric capacitors are arranged in a matrix;
each of the ferroelectric capacitors includes a first signal electrode, a second signal electrode disposed in a direction intersecting the first signal electrode, and a ferroelectric layer disposed at least in an intersection area of the first and second signal electrodes; and
the ferroelectric layer is disposed linearly along one of the first signal electrode and the second signal electrode.
Specifically, the memory cell array may have: (1) a structure in which the ferroelectric layer is selectively disposed over the first signal electrode; or (2) a structure in which the ferroelectric layer is selectively disposed under the second signal electrode.
In this memory cell array, since the ferroelectric layer is formed linearly along one of the first and second signal electrode, the parasitic capacitance or load capacitance of the other of the first and second signal electrodes can be decreased.
According to a second aspect of the present invention, there is provided a second memory cell array having ferroelectric capacitors, wherein: memory cells formed of ferroelectric capacitors are arranged in a matrix; each of the ferroelectric capacitors includes a first signal electrode, a second signal electrode disposed in a direction intersecting the first signal electrode, and a ferroelectric layer disposed at least in an intersection area of the first and second signal electrodes; and the ferroelectric layer is disposed only in the intersection area of the first and second signal electrodes. In this memory cell array, since the ferroelectric layers making up the ferroelectric capacitors are formed in the smallest region, the parasitic capacitance or load capacitance of the signal electrodes can be further decreased.
In this memory cell array, since the ferroelectric layer forming the ferroelectric capacitor has a minimum area, the parasitic capacitance or load capacitance of the signal electrodes can be further reduced.
The above memory cell arrays have the following features.
(A) The ferroelectric capacitors may be disposed on a base; and a dielectric layer may be provided between laminates each of which includes the first signal electrode and the ferroelectric layer so as to cover an exposed surface of the base. In this case, the dielectric layer may be formed of a material having a dielectric constant lower than a dielectric constant of the ferroelectric layer. The parasitic capacitance or load capacitance of the signal electrodes can be reduced effectively by providing such dielectric layer.
(B) An undercoat layer having surface properties differing from surface properties of the base may be formed on the base. By providing such undercoat layer, at least either the signal electrode or the ferroelectric layer can be formed selectively without etching. The undercoat layer may be provided in an area in which the ferroelectric capacitors are not formed; and a surface of the undercoat layer may have a low affinity for a material forming the ferroelectric capacitors, in comparison with a surface of the base. Alternatively, the undercoat layer may be provided in an area in which the ferroelectric capacitors are formed; and a surface of the undercoat layer may have a high affinity for a material forming the ferroelectric capacitors, in comparison with a surface of the base.
According to a third aspect of the present invention, there is provided a method of fabricating a memory cell array in which memory cells formed of ferroelectric capacitors are arranged in a matrix, comprising the steps of:
forming a first signal electrode with a predetermined pattern on a base;
selectively forming a ferroelectric layer on the first signal electrode linearly along the first signal electrode; and
forming a second signal electrode in a direction intersecting the first signal electrode.
This fabrication method may further comprise the steps of: forming on the base a first region having surface properties which give priority in deposition to a material of at least one of the first signal electrode and the ferroelectric layer, and a second region having surface properties which give difficulty in deposition to the material of at least one of the first signal electrode and the ferroelectric layer in comparison with the first region; and providing the material of at least one of the first signal electrode and the ferroelectric layer and selectively forming one of the first signal electrode and the ferroelectric layer in the first region. The first and second regions may be defined on a surface of the base.
In this fabrication method, the surface of the base may be exposed in the first region; and in the second region may be formed an undercoat layer having surface properties having a low affinity for materials of the first signal electrode and the ferroelectric layer in comparison with the exposed surface of the base in the first region. Alternatively, in this fabrication method, the surface of the base may be exposed in the second region; and in the first region may be formed an undercoat layer having surface properties having a high affinity for materials of the first signal electrode and the ferroelectric layer in comparison with the exposed surface of the base in the second region.
According to a fourth aspect of the present invention, there is provided a method of fabricating a memory cell array in which memory cells formed of ferroelectric capacitors are arranged in a matrix, comprising the steps of:
forming a first signal electrode with a predetermined pattern on a base; and
forming a ferroelectric layer and a second signal electrode in a direction intersecting the first signal electrode, wherein the ferroelectric layer is disposed linearly along the second signal electrode.
In this fabrication method, the ferroelectric layer and the second signal electrode may be patterned by etching using the same mask.
According to a fifth aspect of the present invention, there is provided a method of fabricating a memory cell array in which memory cells formed of ferroelectric capacitors are arranged in a matrix, comprising the steps of:
forming a first signal electrode with a predetermined pattern on a base;
forming a ferroelectric layer on the first signal electrode linearly along the first signal electrode;
forming a second signal electrode in a direction intersecting the first signal electrode; and
patterning the ferroelectric layer to be disposed only in an intersection area of the first and second signal electrodes.
In this fabrication method, at least either the signal electrode or ferroelectric layers may be provided by using the above-described undercoat layer. The ferroelectric layers and the signal electrode may be patterned by etching using the same mask.
In each of the above fabrication methods, the dielectric layer may be provided between laminates which include the signal electrode and the ferroelectric layer so as to cover at least an exposed surface of the base.
According to a sixth aspect of the present invention, there is provided a ferroelectric memory device comprising the memory cell array according to the present invention.